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the hitachi HN28F101 is a 131072-word x 8-bit cmos flash memory, realizing on-board programming. it programs or erases data with only on-board power supply (12 v v pp supply/5 v v cc supply). it programs data with fast program- ming algorithm by command inputs. it has two types of erase algorithm : automatic erase and fast erase by command inputs. automatic erase func- tion can erase data automatically without external control only by inputting trigger pulse and inform erase completion to cpu by status polling. the HN28F101 can control programming erase algorithm externally. features on-board power supply (v cc /v pp ) v cc = 5 v 10% v pp = v ss to v cc (read) v pp = 12.0 v 0.6 v (erase/program) fast access time 120 ns/150 ns/200 ns (max) programming function byte programming programming time: 25 ? typ/byte address, data, control latch function on-board automatic erase function chip erase erase time: 1 s typ address, data, control latch function status polling function low power dissipation i cc = 10 ma typ (read) i cc = 20 ? max (standby) i pp = 30 ma typ (auto erase/program) i pp = 20 ? max (read/standby) erasing endurance: 10,000 times pin arrangement: 32-pin jedec standard package 32-pin dip 32-pin sop 32-pin tsop 32-pin plcc ordering information type no. access time package HN28F101p-12 120 ns 32-pin plastic dip HN28F101p-15 150 ns (dp-32) HN28F101p-20 200 ns HN28F101fp-12 120 ns 32-pin plastic sop HN28F101fp-15 150 ns (fp-32d) HN28F101fp-20 200 ns HN28F101t-12 120 ns 32-pin plastic tsop HN28F101t-15 150 ns (tfp-32da) HN28F101t-20 200 ns HN28F101r-12 120 ns 32-pin plastic tsop HN28F101r-15 150 ns (tfp-32dar) HN28F101r-20 200 ns HN28F101cp-12 120 ns 32-pin plcc HN28F101cp-15 150 ns (cp-32) HN28F101cp-20 200 ns HN28F101 series 131072-word 8-bit cmos flash memory
ordering information (cont.) type no. access time package HN28F101td-12 120 ns 32-pin plastic tsop HN28F101td-15 150 ns (tfp-32d) HN28F101td-20 200 ns HN28F101rd-12 120 ns 32-pin plastic tsop HN28F101rd-15 150 ns (tfp-32dr) HN28F101rd-20 200 ns pin arrangement 2 HN28F101 series HN28F101 series HN28F101p/fp series HN28F101cp series 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 i /o0 i /o1 i /o2 v pp ss v we nc a14 a13 a8 a9 a11 oe a10 ce i / o7 i / o6 i / o5 i / o4 i / o3 cc (top view) (top view) a7 a6 a5 a4 a3 a2 a1 a0 i/o0 a14 a13 a8 a9 a11 oe a10 ce i/o7 a12 a15 a16 v v we nc pp cc i/o1 i/o2 v i/o3 i/o4 i/o5 i/o6 ss 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 14 15 16 17 18 19 20 4 3 2 1 32 31 30 pin description pin name function a0-a16 address i/o0-i/o7 input/output ce chip enable oe output enable we write enable v cc power supply v pp programming power supply v ss ground
pin arrangement (cont) 16 12 10 8 6 4 2 15 13 11 9 7 5 3 1 18 20 22 24 26 28 30 32 17 19 21 23 25 27 29 31 a4 a6 a12 a16 v nc a13 a9 a5 a7 a15 v we a14 a8 a11 a3 a1 i / o0 i / o2 i / o3 i / o5 i / o7 a10 a2 a0 i / o1 v i / o4 i / o6 ce oe pp cc ss (top view) 14 HN28F101t/td series 16 12 10 8 6 4 2 15 13 11 9 7 5 3 1 18 20 22 24 26 28 30 32 17 19 21 23 25 27 29 31 a4 a6 a12 a16 v nc a13 a9 a5 a7 a15 v we a14 a8 a11 a3 a1 i / o0 i / o2 i / o3 i / o5 i / o7 a10 a2 a0 i / o1 v i / o4 i / o6 ce oe pp cc ss (top view) 14 HN28F101r/rd series 3 HN28F101 series HN28F101 series
block diagram a5 a12 a9 a16 i/o0 i/o7 address latch x ? decoder 1024 x 1024 memory matrix y ?gating y ?decoder address latch input data control data latch r / w / e control a0 ?a4, a10, a11 h : high threshold inverter h latch ce oe we v cc v pp v ss 4 HN28F101 series HN28F101 series
mode selection pin v pp ce oe we a9 i/o0 ?i/o7 dip, sop, plcc (1) (22) (24) (31) (26) (13 ?15, 17 ?21) mode tsop (9) (30) (32) (7) (2) (21 ?23, 25 ?29) read read v cc *6 v il v il v ih a9 dout output disable v cc v il v ih v ih x high-z standby v cc v ih x x x high-z identifier *1 v cc v il v il v ih vh *2 id command read *3,*5 v pp v il v il v ih a9 dout program output disable v pp v il v ih v ih x high-z standby v pp v ih x x x high-z write *4 v pp v il v ih v il a9 din notes: 1. device identifier code can be output in command programming mode. refer to the table of command address and data input. 2. v h : 11.5 < v h < 12.5v. 3. data can be read when 12 v is applied to v pp . device identifier code can be output by command inputs. 4. refer to the table of command address and data input. data is programmed, erased, or verified after mode setting by command inputs. 5. status of automatic erase can be verified in this mode. status outputs on i/o7. i/o0 to i/o6 are in high impedance state. 6. x : v ih or v il . v pp = 0 v to v cc 5 HN28F101 series HN28F101 series
command address and data input first cycle second cycle the number operation address *2 data *3 operation address *2 data *3 command of cycle mode *1 mode *1 read (memory) *4 1 write x 00h read ra dout read identified codes 2 write x 90h read ia id setup erase/erase *5 2 write x 20h write x 20h erase verify *5 2 write ea a0h read x evd setup auto erase/ 2 write x 30h write x 30h auto erase *6 setup program/ 2 write x 40h write pa pd program *7 program verify *7 2 write x c0h read x pvd reset 2 write x ffh write x ffh notes: 1. refer to command program mode in mode selection about operation mode. 2. refer to device identifier mode. ia = identifier address, pa = programming address, ea = erase verify address, ra = read address 3. refer to device identifier mode. pa are latched by programming command. id = identifier output code, pd = programming data, pvd = programming verify output data, evd = erase verify output data 4. command latch default value when applying 12 v to v pp is ?0h? device is in read mode after v pp is set 12 v (before other command is input). 5. all data in chip are erased. erase data according to fast high-reliability erase flowchart. 6. all data in chip are erased. data are erased automatically by internal logic circuit. external erase verify is not required. erasure completion must be verified by status polling after automatic erase starts. 7. program data according to fast high-reliability programming flowchart. 6 HN28F101 series HN28F101 series
absolute maximum ratings parameter symbol value unit all input and output voltage *1 vin, vout ?.6 *2 to +7.0 v v pp voltage *1 v pp ?.6 to +14.0 v v cc voltage *1 v cc ?.6 to +7.0 v operating temperature range topr 0 to +70 ? storage temperature range *3 tstg ?5 to +125 ? storage temperature under bias tbias ?0 to +80 ? notes: 1. relative to v ss . 2. vin, vout, v id min = ?.0 v for pulse width < 20 ns. 3. device storage temperature range before programming. capacitance (ta = 25?, f = 1 mhz) parameter symbol min typ max unit test condition input capacitance cin 6 pf vin = 0 v output capacitance cout 12 pf vout = 0 v 7 HN28F101 series HN28F101 series
read operation dc characteristics (v cc = 5 v 10%, v pp = v cc~ v ss , ta = 0 to +70?) parameter symbol min typ max unit test condition input leakage current i li 2 a vin = 0 to v cc output leakage current i lo 2 a vout = 0 to v cc v pp current i pp1 20 ? v pp = 5.5 v standby v cc current i sb1 1 ma ce = v ih i sb2 20 ? ce = v cc operating v cc current i cc1 6 15 ma iout = 0 ma, f = 1 mhz i cc2 10 30 ma iout = 0 ma, f = 8 mhz input voltage *3 v il ?.3 *1 0.8 v v ih 2.2 v cc + 0.3 *2 v output voltage v ol 0.45 v i ol = 2.1 ma v oh 2.4 v i oh = ?00 ? notes: 1. v il min = ?.0 v for pulse width < 20 ns. 2. v ih max = v cc + 1.5 v for pulse width < 20 ns. if v ih is over the specified maximum value, read operation cannot be guaranteed. 3. only defined for dc and long cycle function test. v il max = 0.45 v, v ih min = 2.4 v for ac function test. 8 HN28F101 series HN28F101 series
ac characteristics (v cc = 5 v 10%, v pp = v ss to v cc , ta = 0 to +70?) test conditions HN28F101-12 HN28F101-15 HN28F101-20 test parameter symbol min max min max min max unit condition address to output delay t acc 120 150 200 ns ce = oe = v il ce to output delay t ce 120 150 200 ns oe = v il oe to output delay t oe 60 70 80 ns ce = v il oe high to output float *1 t df 040050060ns ce = v il address to output hold t oh 555 ns ce = oe = v il note: 1. t df is defined as the time at which the output achieves the open circuit condition and data is no longer driven. read timing waveform ce t ce t oe t acc t oh t df standby mode active mode standby mode high address oe we data out data out valid input pulse levels: 0.45 v/2.4 v input rise and fall times: 10 ns output load: 1ttl gate + 100 pf (including scope and jig.) reference levels for measuring timing: 0.8 v, 2.0 v 9 HN28F101 series HN28F101 series
command programming/data programming/erase operation dc characteristics (v cc = 5 v 10%, v pp = 12.0 v 0.6 v, ta = 0 to +70?) parameter symbol min typ max unit test condition input leakage current i li 2 a vin = 0 v to v cc output leakage current i lo 2 a vout = 0 v to v cc standby v cc current i sb1 1 ma ce = v ih i sb2 200 ? ce = v cc operating read i cc1 6 15 ma iout = 0 ma, f = 1 mhz v cc current i cc2 10 30 ma iout = 0 ma, f = 8 mhz program i cc3 2 10 ma erase i cc4 10 40 ma in automatic erase i cc5 5 15 ma in high-reliability erase v pp current read i pp1 1 mav pp = 12.6 v program i pp2 5 30 ma in programming erase i pp3 35 80 ma in automatic erase i pp4 10 30 ma in high-reliability erase input voltage v il ?0.3 *4 0.8 v v ih 2.2 v cc + 0.3 *5 v output voltage v ol 0.45 v i ol = 2.1 ma v oh 2.4 v i oh = ?00 ? notes: 1. v cc /v pp power on/off timing v cc must be applied before or simultaneously v pp , and removed after or simultaneously v pp . this v cc /v pp power on/off timing must be satisfied at v cc /v pp on/off caused by power failure. 2. v pp must not exceed 14 v including overshoot. 3. an influence may be had upon device reliability if the device is installed or removed while v pp = 12 v. 4. v il min = ?.0 v for pulse width < 20 ns. 5. if v ih is over the specified maximum value, programming operation cannot be guaranteed. 0? min 0? min 0v 5v 12v 5v 0v v cc v pp 10 HN28F101 series HN28F101 series
ac characteristics (v cc = 5 v 10%, v pp = 12.0 v 0.6 v, ta = 0 to +70?) test condition HN28F101-12 HN28F101-15 HN28F101-20 test parameter symbol min max min max min max unit condition command programming cycle tim et cwc 120 150 200 ns address setup time t as 000ns address hold time t ah 60 60 60 ns data setup time t ds 50 50 50 ns data hold time t dh 10 10 10 ns ce setup time t ces 000ns ce hold time t ceh 50 50 50 ns v pp setup time t vps 100 100 100 ns v pp hold time t vph 100 100 100 ns we programming pulse width t wep 70 70 80 ns we programming pulse high time t weh 40 40 40 ns oe setup time before command t oews 000ns programming oe setup time before verify t oers 666s verify access time t va 120 150 200 ns verify access time in erase t vae 300 300 300 ns oe setup time before status polling t oeps 120 120 120 ns status polling access time t spa 120 150 200 ns standby time before programming t ppw 25 25 25 s standby time in erase t et 911911911ms output disable time *3 t df 040050060ns total erase time in automatic erase *3 t aet ?030?0s input pulse levels: 0.45 v/2.4 v input rise and fall times: 10 ns output load: 1ttl gate + 100 pf (including scope and jig.) reference levels for measuring timing: 0.8 v, 2.0 v 11 HN28F101 series HN28F101 series
12 HN28F101 series HN28F101 series notes: 1. ce , oe , and we must be fixed high during v pp transition from 5 v to 12 v or from 12 v to 5 v. 2. refer to read operation when v pp = v cc about read operation while v pp = 12 v . 3. t df is defined as the time at which the output achieves the open circuit condition and data is no longer driven. 4. address are taken into on the falling edge of write-enable pulse and addresses are latched on the rising edge of write-enabke pulse during chip-enable is low. data is latched on the rising edge of write-enable pulse during chip-enable is low. erase and program time erase and program mode min typ *4 max unit chip (128 kb) erase time auto erase mode 1 30 second fast high-reliability erase mode *2, 3 0.6 30 second chip (128 kb) program time fast high-reliability program mode *3 ? 81 *5 second notes: 1. each values are same for all read access version. 2. excludes pre-write process before erasure and verify process (6 ? x 128 kb). 3. excludes system overhead. 4. ta = 25?, v pp = 12 v, v cc = 5 v 5. theoretical value calculated from fast high-reliability programming flowchart. (25 ? program + 6 ? verify) x 20 times x 128 kb = 81 second.
automatic erase timing waveform 13 HN28F101 series HN28F101 series t ceh t ces t oeps t wep t ces t cwc t wep t ds t dh t ds t dh t spa t df t vph t ces t ceh setup auto erase auto erase & status polling status polling 5.0 v v cc 12 v 5.0 v v pp address ce oe we i / o7 i / o0 ?i / o6 t aet t oews t vps command in command in command in command in t weh status polling status polling allows the status of the flash memory to be determined. if the flash memory is set to the status polling mode during erase cycle, i/o 7 pin is lowered to v ol level to indicate that the flash memory is performing erase operation. i/o 7 pin is set to the v oh level when erase operation has finished. notes: in automatic erase mode, the device automatically processes to pre-write all ??before erasing. therefore, it is not required to pre-write by fast high-reliability programming.
fast high-reliability programming flowchart notes: in case of two or more devices are programmed simultaneously, following steps should be apllied to avoid over programming for the verified device . (1) write set up program command to ffh, (2) write program command to ffh, (3) write program verify command to 00h and program verify address to read address. start apply v = 12.0 ?0.6 v pp address = 0 n = 0 n + 1 n write setup program command write program address and data wait 25 s write program verify command wait 6 s verify last address ? apply v = v end pp cc address + 1 address n = 20 fail nogo no yes yes go no ? ? m m fast high-reliability programming this device can be applied the fast high-reliability programming algorithm shown in following flowchart. this algorithm allows to obtain fasterprogramming time without any voltage stress to the device nor deterioration in reliability of programmed data. 14 HN28F101 series HN28F101 series
fast high-reliability programming timing waveform wep t vps t as t ah t ces t oews t wep t cwc t t ces t t ceh t dh t ds t dh t ds t ds t dh t ces t wep t ceh t oers t va t df t vph setup program program verify 5.0 v 12 v 5.0 v address v cc v pp ce oe we i / o7 i / o0 to i / o6 data out valid data out valid command in command in command in command in data in data in t weh t ppw t ppw t ppw t ppw t ppw address valid ceh program notes: the data output level during program verification may result in an intermediate level between v oh and v ol due to an insufficiently programmed. 15 HN28F101 series HN28F101 series
16 HN28F101 series HN28F101 series fast high-reliability erase this device can be applied the fast high-reliability erase algorithm showm in following flowchart this algorithm allows to abtain faster erase time without any voltage any voltage stress to the device nor deterioration in reliability of data. fast high-reliability erasing flowchart notes: in case of two or more devices are erased simultaneously, following steps should be applied to avoid over erase for verified device. (1) write set up erase command to a0h and set erase verify address to verify address. (2) write erase command to a0h. (3) write erase verify command to a0h. start all bits program 00h *1 n = 0 n + 1 n write setup erase / erase command wait 10 ms write erase verify command wait 6 s verify last address ? end address + 1 address n = 3000 fail no yes yes yes no no ? *1. program data to all bits according to fast high-reliability erasing flowchart. set address all bits data = 00h? no yes
17 HN28F101 series HN28F101 series t ces 5.0 v 12 v address v cc v pp ce oe we t wep t cwc t ceh t ces t ds t dh t ds t dh t ds t wep t ceh t ces t et t t ceh t oers t vae t df t vph t oews t as t ah setup erase erase erase verify data out valid command in t vps 5.0 v i/o0 to i/o7 t weh dh t wep command in command in address valid notes: the data output level during erasure verification may result in an intermediate level between v oh and v ol due to an insufficiently erased. erase timing waveforms
mode description device identifier mode the device identifier mode allows the reading out of binary codes that identify manufacturer and type of device, from outputs of flash memory. by this mode, the device will be automatically matched its own corresponding erase and programming algorithm, using programming equipment. HN28F101 series identifier code 18 HN28F101 series HN28F101 series pins a0 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 hex dip. sop, plcc (12) (21) (20) (19) (18) (17) (15) (14) (13) identifier tsop (20) (29) (28) (27) (26) (25) (23) (22) (21) data manufacturer code v il 0000011 107 device code v ih 0001100 119 notes : 1. device identifier code can be read out by applying 12.0 v ?.5 v to a9 when v pp = v cc , or inputting command while v pp is 12 v. 2. a1 to a8, a10 to a16, and ce = oe = v il , we = v ih 3. v cc = v pp = 5 v ?0%

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